Returns true only for the active lane in the current wave with the smallest index Returns the index of the current lane within the current wave. Returns the number of lanes in the current wave. The intrinsics for querying a single wave. The output of such a lane will be discarded, and so not render to the destination surface.Īll the operations of this shader model have been added in a range of intrinsic functions. All pixels in an active quad are executed (and may be "Active Lanes"), but those that do not produce visible results are termed "Helper Lanes".Ī lane which is executed solely for the purpose of gradients in pixel shader quads. A wave may be comprised of multiple quads. They are used to estimate gradients by differencing in either x or y. In pixel shaders, it may include any helper pixel lanes.Ī set of 4 adjacent lanes corresponding to pixels arranged in a 2x2 square. Similar concepts include "warp" and "wavefront."Ī lane which is not being executed, for example due to the flow of control, or insufficient work to fill the minimum size of the wave.Ī lane for which execution is being performed.
No explicit barriers are required to guarantee that they execute in parallel. The shader models before version 6.0 expose only one of these at the language level, leaving expansion to parallel SIMD processing entirely up to the implementation.Ī set of lanes (threads) executed simultaneously in the processor. Terminology TermĪ single thread of execution. Some operations (such as the bitwise operators) only support the integer types. The parameter and return value for these functions implies the type of the expression, the supported types are those from the following list that are also present in the target shader model for your app: The functions have been added to the requirements for DirectX Feature Level 12.0, under API level 12. Most of the intrinsics appear in pixel shaders and compute shaders, though there are some exceptions (noted for each function). Potential use cases include: stream compaction, reductions, block transpose, bitonic sort or Fast Fourier Transforms (FFT), binning, stream de-duplication, and similar scenarios. For example, the model 6.0 intrinsics enable the elimination of barrier constructs when the scope of synchronization is within the width of the SIMD processor, or some other set of threads that are known to be atomic relative to each other. New wave-level operations are provided, starting with model 6.0, to explicitly take advantage of the parallelism of current GPUs - many threads can be executing in lockstep on the same core simultaneously. Describes the wave operation intrinsics added to HLSL Shader Model 6.0.įor earlier shader models, HLSL programming exposes only a single thread of execution.
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